Real-time simulation of CDSM modular multilevel converter for HIL test applications

Recently, a few modular multilevel converter (MMC) projects were commissioned around the world. In some planning projects, the DC links are overhead lines, therefore the DC fault current limitation capability becomes a concern. The MMC using clamp double submodule (CDSM) topology can naturally limit the DC fault current and is a good option for those projects. From experience with previous projects, the real time hardware-in-the-loop (HIL) test bench played an important role in validating the manufacturer's controllers. Since the CDSM has more complicated topology than the half-bridge (HB) or full-bridge (FB) submodule (SM), previously no MMC CDSM model is available for HIL test benches. This paper presents an equivalent circuit method to model and simulate CDSM MMC systems with sufficient detail, accuracy, speed, and I/O connectivity that satisfies the HIL test requirements. The MMC valves in the main circuit are replaced by the simple equivalent circuit and the SM are implemented and solved in field-programmable gate array (FPGA) or multiple CPU in parallel. The model can simulate very large CDSM systems in real time speed. The results of a demo CDSM MMC system are provided in the paper. The test bench based on this method has been provided to some MMC controller manufacturers for their study and tests.