DPSK Signal Carrier Synchronization Module Implemented on the FPGA

This paper proposes a method to implement the modified square loop digitally on the FPGA to solve the problem, that the divide circuit in the traditional square loop is difficult to achieve. The modified square loop has a similar structure to the traditional square loop. The method of modified square loop is to multiply quadrature output together to replace the divide circuit. In this paper, a specific method is given to digitize the square loop. The output carrier signal and the frequency difference will be analyzed in the condition of different initial frequency offset, parameters of the loop filter and input SNR.