A Mask-Misalignment Offset Reduction Method for Design of Cross-Like CMOS Hall Devices

The mask-misalignment offset, as an inevitable part of the initial offset, is necessary to be reduced in the design of cross-like Hall devices. In this paper, a method is proposed to reduce the mask-misalignment offset. In order to find the method to reduce the mask-misalignment offset, the Hall sensors of different sizes and with different N-type doping regions are simulated by Silvaco Technology Computer Aided Design simulator. The Hall devices of different sizes have the same ratio of length and width, making the geometrical factor unchanged. The two different N-type doping regions are extracted from the 0.18 µm BCDliteTM technology provided by GLOBALFOUNDRIES. We found out the effects of different sizes and different N-type doping active regions on the offset.