Highly linear fully integrated class-O power amplifier in standard 65 nm CMOS technology

This paper demonstrates a fully integrated class-O power amplifier (PA), as a stand-alone module. The PA is implemented in a standard 65 nm CMOS including input matching, load-transformation networks and baluns. Thus, no extra lumped components are needed. The class-O PA consists of a common-drain (CD) and a common-source (CS) amplifier. The CD provides excellent linearity due to the inherent feedback but low gain at RF frequency. The CS is employed to increase the gain. Capacitive-feedback is used to improve the stability of the class-O PA. Measured saturated output power (P_out) is 26.7 dBm and peak PAE is 26.2 % at 2.26 GHz under a Vdd of 2.5 V for the fabricated PA module, i.e. PCB and bonding losses are included. With a 64 QAM LTE, 20 MHz signal applied an average Pout of 18.8 dBm is obtained while E-UTRA ACLR is below -30 dBc without DPD. An average P_out of 22.5 dBm and EVM of 4.5 % are achieved with WCDMA standard.

I. Introduction

Complicated modulation schemes and OFDM are popularly employed in modern communication standards (e.g. WCDMA, LTE, WiFi) to achieve high-data-transmission rates in a limited bandwidth. In these standards, however, the peak-to-average power ratio (PAPR) is high. Therefore, power amplifiers (PAs) using III-V semiconductor are widely adopted resulting in higher cost compared to bulk CMOS solutions, particularly in user terminations.