Fabrication of PVD-TiN metal-gate SOI-CMOS integrated circuits using minimal-fab and mega-fab hybrid process

The PVD-TiN metal-gate SOI-CMOS integrated circuits including inverters and ring oscillators have successfully been fabricated on a half-inch (100)-oriented SOI wafer using the minimal-fab and mega-fab hybrid process, and their electrical characteristics have systematically been investigated. It was experimentally found that almost an ideal subthreshold slope (SS) of 67 mV/decade and an extremely low leakage current (<;1×10
^-13
A), and the almost a symmetrical threshold voltage (|V
_t
|) for P- and N-channel devices due to the midgap work function of the PVD-TiN are obtained in the fabricated SOI-CMOS devices. Moreover, it was confirmed that the fabricated 41-stage ring oscillators show normal operations at different supply voltages and the oscillation frequencies are close to the estimated values by gate capacitances and drive currents. These excellent results indicate that the developed minimal-fab and mega-fab hybrid process is suitable for the fabrication of conventional CMOS integrated circuits.