Design and implementation of high performance advanced extensible interface(AXI) based DDR3 memory controller

This paper deals with the designing an interface between AXI Protocol based system and DDR3 Memory. It enables an AXI host to read and write data in a DDR3 Memory. It has been designed to utilize the DDR3 interface for maximum throughput. It implements FIFO where it stores the write command and writes data and passes it to DDR3 Memory. Similarly, it collects data from DDR3 Memory and stores in a FIFO which it sends to host whenever it is ready to accept data. The design throughput has been increased.