CLA based 32-bit signed pipelined multiplier

In this paper, Radix-4 Modified Booth Encoding (MBE) is used to generate partial product. The proposed 32-bit multiplier is based on pipelining. The main target is to reduce the delay of higher bits multiplier and speeding up the computation. The proposed design is implemented in Xilinx 14.2. The delay achieved is 2.826ns for computing 32×32 bit signed multiplication with maximum frequency of 353.832 MHz on the device 7vx330tffg1157-3.