R-2R ladder circuit design for 32-bit digital-to-analog converter (DAC) with noise analysis and performance parameters

In modern ICs, signal circuits like ADCs and DACs plays an important role in mixed signal processing. There are thousands of times that you need a signal in analog form. For example to process a signal or data generated by any computer there may be need a signal of an analog form. A simple example of it is a conversion of computer data into Audio-Frequency tones needs for telephony. This function is done by the circuit called DAC. There are numbers of DACs available which may of M-number of bits. In this paper a simple way to design a DAC with register networks (R-2R) is presented. R-2R ladder systems give a straightforward intends to change over digital data to an analog yield. The performance of the R-2R DAC in terms of efficiency or resolution is the major issue of this type of network Due to mismatching of resistor the performance of R-2R is somehow limited although this type of ladder can be realized as a ICs (Integrated Circuits). Calibration is one of the method by which Integral and Differential Non-Linearities can be reduced. Low noise performance of the resistor ladder (R-2R) DAC, allows it to be used in high performance audio solution. Compensation of DNL and INL nonlinearities are possible somehow even though static distortions are the most often in high end ladder network digital to analog converter. In this paper, 32-bit DAC is presented with noise voltage analysis and other performance parameters, theoretical and simulation in microwind 3.1 with noise voltage analysis is also presented.