Performance and reliability analysis for VLSI circuits using 45nm technology

Performance and reliability analysis tests the VLSI circuits over a prolonged period of time at different conditions. Therefore, performance and reliability of an inverter circuit and two CMOS gate interconnect circuit, a combination of two inverters connected with an RC model as an interconnect structure has been analyzed. Reliability in VLSI circuits depends on hot carrier injection, negative biasing temperature instability, positive biasing temperature instability and time-dependent gate oxide breakdown. Reliability is analyzed by comparing power, delay and output voltage. The complete analysis is done using 45nm gpdk (generic process design kit) in Cadence Virtuoso.