A review on VLSI floorplanning optimization using metaheuristic algorithms

In the VLSI physical design, floorplanning is an essential design step, as it determines the size, shape, and locations of modules in a chip and as such it estimates the total chip area, the interconnects, and, delay. Computationally, VLSI floorplanning is an NP hard problem. So many researchers have suggested various heuristics and metaheuristic algorithms to solve the VLSI floorplan problem. The representation of floorplan is an important aspect of the floorplanning Stage. The floorplan representations have an important impact on the complexity and search space of the floorplan design. In this paper, we included studying and comparing PSO, SA and ACO as optimization algorithms for floorplanning and the representations involved in the VLSI floorplanning problem.