Low-Power and High-Performance Ternary SRAM Designs With Application to CNTFET Technology

This paper presents two efficient ternary SRAM designs appropriate for several transistor-based technologies. The first design is based on the cycle operator in ternary logic while the second is a buffer-based design that employs the positive and negative ternary inverters. Both the designs consume low power in comparison to existing standard ternary inverter-based SRAM designs. Further, the read and write delay for the proposed designs are much lower than the corresponding ones for existing designs. Detailed analyses of the proposed circuits are presented. Extensive HSpice simulations (and comparisons) using a Carbon Nanotube Field Effect Transistor library are reported. The proposed designs also have noise margins comparable to existing designs.