Investigation of Temperature and Source/Drain Overlap Impact on Negative Capacitance Silicon Nanotube FET (NC Si NTFET) with Sub-60mV/decade Switching

In this paper, the impact of temperature and source/drain overlap on DC characteristics and analog/RF performance of the negative capacitance silicon nanotube FET (NC Si NTFET) have been presented. The performance of the device is examined by coupling the 3D TCAD numerical simulation with 1D Landau-Khalatnikov (LK) equation. The effect of negative capacitance has been investigated for different source/drain overlap lengths (L
_ov
) at 300 K and 380 K. The optimal values of source/drain overlap lengths and effective ferroelectric thickness (t
_f
) have been found to attain significant improvement in device performance in terms of drain current (I
_d
), subthreshold swing (SS), gate capacitance (C
_g
), and cut-off frequency (f
_t
). It is reported that a minimum SS of 30.7 mV/decade, and maximum f
_t
of 2.35 THz are achieved for NC Si NTFET at 300 K for an operating frequency of 1 GHz. It is observed that the core (inner gate) radius (t
_c
) can be used to increase the minimum SS and I
_ON
to delay the hysteresis and to achieve a better drive current.