An Optimized Resistance Characterization Technique for the Next Generation Magnetic Random Access Memory

This paper presents an accurate resistance characterization technique for magnetic random access memory (MRAM), such as STT-MRAM. By annulling the mismatch effect of CMOS transistors, this technique produces a resistance distribution profile of MRAM devices in a large array that reflects the actual device statistics. A 1 Kb array of MTJs with an intrinsic 3σ low resistance state distribution modeled with Verilog-A provides the reference device statistics. Monte Carlo simulation results of popular array configurations show the method's generic advantages of tightened distributions of the mean resistance value and standard deviation (SD) of the characterized 1 Kb devices than the reference method. Technology scaling study shows the sustainability of the proposed method with an improvement of the SD of the mean resistance distribution by at least 37.6%. The mean and SD of the standard deviation distribution were improved by at least 25.1% and 67.2% as compared to the reference method, respectively.