Impact of Charge Trapping On Epitaxial p-Ge-on-p-Si and HfO2 Based Al/HfO2/p-Ge-on-p-Si/Al Structures Using Kelvin Probe Force Microscopy and Constant Voltage Stress

The quest for the high speed, low power digital logic circuits urge an imperative demand of compatible high-κ dielectric integration on novel Germanium (Ge) based channel material. Here, first ever a methodical nanoscopic and microscopic probes were attempted to Atomic Layer Deposited, Hafnium Dioxide (HfO
₂
) dielectrics on Molecular Beam Epitaxy (MBE) of p-Ge
_-on-
p-Si stack. Kelvin Probe Force Microscopy based contact potential difference (CPD) analysis reveals that the disintegration of trapped charges lasting for ~18 hours. The impact of constant voltage stress (CVS) on trapped charges results in variation of threshold voltage (V
_th
) and hysteresis window (W) were studied. The cyclic Capacitance-Voltage (C-V) characteristics at 0.5 MHz exhibit the shift in the flat band (ΔV
_fb
), ΔV
_th
, and ΔW at 10V stress were ~0.84V, ~0.62V, and ~0.47V, respectively. While the computed interface trap density (D
_it
) and total effective charge density (Q
_eff
) were ~8.49 × 10
¹²
eV
^-1
cm
^-2
and ~1.81 × 10
¹²
cm
^-2
_,
respectively. The gate leakage current density, (J) at 5V is 26.53 × 10
^-6
A/cm
²
and reduced by a factor of ~6.8 after 10V, CVS. Whereas the current density (J) increases from ~26.53 × 10
^-6
A/cm
²
at 25 °C by a factor of ~2 at 125 °C. To study the retention and effect of charge trapping, the stress-time analysis was performed for 8000s at 3V (CVS). The r.m.s. surface roughness of HfO
₂
thin films was found to be ~0.23 nm. X-ray photoelectron spectroscopy (XPS) depth profiling categorized the elemental composition of thin films. These investigations would help to HfO
₂
/p-Ge
_-on-
p-Si system interfacial engineering well before the Ge based nano device realization.