21T Ternary Full Adder Based on Capacitive Threshold Logic and Carbon Nanotube FETs

The reduction in transistor count has long been a big challenge and an ongoing objective in the design of Ternary Full Adders (TFAs). Capacitive Threshold Logic (CTL) is a well-known logic style requiring a small number of transistors to implement a circuit. This paper presents a novel CTL TFA that utilizes only 21 transistors, three of which function as capacitors. Reducing the number of transistors can achieve a more compact adder cell with fewer internal wires. Simulations by HSPICE and 32nm CNFET technology demonstrate promising results for the new TFA compared to previous competitors. It produces the output carry at the fastest speed and also utilizes six fewer transistors and three fewer nets than its closest competitor with the fewest elements. When a comprehensive evaluation factor including delay, power, and area is considered, the proposed design exhibits a performance superiority of 45.1% and 21.4% compared to the previous top-performing CTL and non-CTL designs, respectively.

I. Introduction

Among various arithmetic circuits, Full Adder (FA) is of utmost importance due to the fact that the functionality of almost every computing datapath depends on this essential block. Addition plays a key role in many of today's cutting-edge applications such as artificial intelligence, machine learning, image and video processing, cryptography, and so forth. This is why circuit designers have been putting so much effort into designing a high-performance FA in different technologies. Several adders have been presented in the literature by using Fin Field Effect Transistors (FinFETs) [1], Carbon Nanotube FETs (CNFETs) [2], Magnetic Tunnel Junctions (MTJs) [3], and memristors [4].