All-Digital Phase-Locked Loop in Single Flux Quantum Circuit Technology

Single flux quantum (SFQ) technology is one of the promising candidates for next generation very large-scale integration circuits. This article presents the design of an all-digital phase-locked loop (PLL) using the rapid SFQ technology with all the functional blocks implemented digitally, including the phase detector, controlled oscillator, loop filter, and frequency divider. A tunable delay cell is designed for the digital controlled oscillator, and Monte Carlo simulations are performed on the extracted postlayout netlist to confirm the functionality and robustness of the design. The all-digital PLL structures are explained and the system transfer function is derived. Circuit simulation shows correct function of the PLL producing a 50-GHz output signal with
$\text{2.93}\,\text{ps}$
peak-to-peak jitter and
$489\text{ fs}$
rms jitter, consuming
$\text{0.45}\,\text{mW}$
. The layout of the PLL is also presented, which shows that the complete design takes an area of
$\text{7.76}\,\text{mm}^2$
, using the MIT Lincoln Lab’s SFQ5ee process.