Finding and Eliminating Noise and Interference in a Test Stand for Josephson Digital Chips

Sources of noise and interference in a test stand for Josephson digital integrated circuits have been identified and eliminated using a novel measurement technique. The digital output of the chip was fed into a spectrum analyzer while the output pattern was 1010. The DC bias was set at the boundary between correct and incorrect operation, a 50% bit error rate. Small AC noise currents on the bias made large changes in the bit error rate. This converted noise currents to amplitude modulation sidebands of the data pattern at half of the logic clock frequency, which was 625 MHz. AC currents were injected at 454 Hz to produce AM sidebands at 625 MHz ± 454 Hz. The sideband power was directly proportional to calibration tone power over the range 50 nA to 10 μA. Noise currents on the DC bias as small as 100 nA were clearly identified at 120 Hz. The largest noise currents in the test setup were found near 40 MHz. Their spectrum of evenly spaced tones indicated that the source was a switching power supply. When an idle relay controller was turned off, the noise tones immediately disappeared from the spectrum analyzer display, confirming the source of interference. This new and easy to use technique exploited bit error rate modulation to up convert AC noise currents from low frequencies to the range 625–675 MHz. The location of the noise currents was unambiguous, since only a 60 Hz noise current on the chip could produce an AM sideband at 625 MHz plus 60 Hz.