Increasing Chip-to-Substrate Spacing Using in Capped SnPb Pillars as Flip Chip Interconnects for Physical Isolation in Superconducting Applications

This work introduces a superconducting interconnect structure consisting of SnPb pillars capped with In to achieve a greater bonding gap between a flip chip and bottom substrate while maintaining a superconducting path. The performance of these new interconnects is demonstrated through electrical characterizations of daisy chain structures at cryogenic temperatures. A 5 mm × 5 mm chip contains six daisy chains totaling 1156 interconnects with a pillar diameter of 50 µm, a pitch of 150 µm, and a pillar height of
$\sim$
50 µm. These pillars can be used as a design tool to mitigate interactions with the bottom substrate dielectrics as well as designing an application dependent capacitance between signals in quantum systems.