A Local Optimization Method for Single Flux Quantum Logic Circuits Design Utilizing Synchronizer IPs

In the post-Moore era, slow-growing operating frequency and massive power dissipation make researchers seek new developing directions in integration circuits (ICs). The single flux quantum (SFQ) circuit, a type of superconducting digital circuit, is regarded as an alternative circuit for future computing technology. SFQ circuits are natural gate-level-pipelining synchronous sequential circuits requiring path balancing. However, path balancing may consume enormous resources, as the logic levels of fan-in gates of most gates are different, with the consumption originating from the extra gates (D-Flip-Flops, DFFs) for path balancing and the routing with a much larger clock tree. Hence, in this article, we propose a local optimization method to address the vast consumption problem of the clock tree caused by path balancing in SFQ circuits, primarily relying on self-developed electronic design automation tools for the JSICcomplier for SFQ circuits and using the SIMIT Nb03 cell library. Moreover, we design synchronizer IPs called Dsyn series to replace DFFs in path balancing. The clock nodes and the clocking path consumption are highly reduced by utilizing the proposed strategy, while the new series can be recognized as IPs and easily added to our library, affording scalability. Experiments in a demo S-box circuit demonstrated a percentage of Josephson junctions reduction in clock tree up to 36.48%, while on a few benchmark circuits, the corresponding results are up to 50.69%, demonstrating our method's effectiveness.