I. Introduction
Superconducting rapid single-flux-quantum (RSFQ) circuit technology [1] and its energy-efficient derivatives [2], [3], [4], [5] have been attracting much attention due to their low-power consumption and high-speed operation. Several gate-level-pipelined high-throughput RSFQ circuits with the structure as shown in Fig. 1 have been designed and demonstrated [6], [7], [8], [9]. In such RSFQ circuits, gates are placed in columns according to their logic level and connected with Passive Transmission Lines (PTLs) [10] routed in the routing area between adjacent columns. The signal transmission delay on a PTL is linearly proportional to its wire length. These circuits are designed with concurrent-flow clocking scheme, where the operating frequency is increased by minimizing the maximum difference among the signal transmission delays in each routing area. The length of PTLs is adjusted by wire length-matching at all logic gates.
Structure of a high-throughput gate-level-pipelined RSFQ circuits.