Striking a Good Balance Between Area and Throughput of RSFQ Circuits Containing Feedback Loops

Electronic design automation solutions are being developed to support the synthesis and physical design optimization of Rapid Single Flux Quantum (RSFQ) logic circuits with hundreds of thousands of logic cells. The clocked feature of synchronous RSFQ cells results in gate-level pipelined designs, requiring a large number of path-balancing D-flipflops (DFFs). In addition, one also faces the challenge of maintaining high throughput for RSFQ circuits containing feedback loops. To enforce the coincidence of the input and feedback patterns, one can apply a new input pattern every
$L$
cycles, where
$L$
is the length of the feedback loop. Consequently, the throughput of circuits with feedback loops is only
$1/L$
of the clock frequency. In this paper, we present two methods to improve the performance and area of RSFQ circuits, especially targeting circuits with feedback loops: (i) An area-oriented optimization method that removes the path-balancing DFFs by capturing and repeating input patterns. (ii) A throughput-oriented optimization method that enables an RSFQ circuit to receive and correctly process an input pattern every clock cycle. For a large circuit such as S526 in the ISCAS89 benchmark circuits, the circuit can initially receive an input pattern only every 9 cycles. As a result of applying our area-oriented optimization, the circuit admits 33% fewer logic cells while receiving input patterns every 11 cycles. Alternatively, our throughput-oriented optimization yields a circuit that can receive new input patterns on every cycle with nearly the same cell count.