4K Real-Time HEVC Decoder on an FPGA

With the popularization of a quad high-definition/4K video being dependent on the availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware implementations have become more appealing due to their superior performance and low power consumption. In this paper, a field-programmable gate array (FPGA)-based hardware implementation of a 4K 30 frames/s real-time HEVC decoder is presented. An elastically pipelined decoder architecture is used to absorb variations in processing time and each pipeline stage is optimized to use available FPGA primitives. FPGA-specific challenges in managing critical path delays to achieve a target operating frequency of 150 MHz required many architectural novelties, such as exploitation of the sparsity of transformed coefficient matrix, single-cycle reference pixel processing in intra prediction, and flexible $8 \times 8$ block ordering in deblocking filter/sample adaptive offset filter. A high-throughput latency-aware cache architecture was used to reduce the external dynamic RAM access bandwidth by 70%. This work is compliant with the HEVC main profile at level 5 of the HEVC standard and only consumes 126K lookup tables, 58K registers, and 335 18-kb block RAMs when implemented on Xilinx Zynq 7045.

I. Introduction

High Efficiency Video Coding (HEVC) is the latest video compression standard introduced by International Organization for Standardization/International Electrotechnical Commission and Telecommunication Standardization Sector of the International Telecommunications Union in early 2013, as an effort to address the issue of ever-growing demand for transmission and storage of a high-resolution video. HEVC promises up to 50% bitrate reduction over the incumbent H.264, but at the cost of extra computational complexity. With the video industry now moving toward quad high-definition (QHD/4K) (), which contains four times more video data than high-definition (HD) video, it is expected that HEVC will become the video codec of choice in the future. With the growing popularity of HD and QHD video and the increased computational complexity, the added resource usage and power consumption of software HEVC decoders place them at a disadvantageous position. Therefore, hardware decoders are preferred especially in low-power mobile applications.