NBTI aging evaluation of PUF-based differential architectures

Silicon Physical Unclonable Functions (PUFs) have emerged as novel cryptographic primitives, with the ability to generate unique chip identifiers and cryptographic keys by exploiting intrinsic manufacturing process variations. The “Two Choose One” PUF (TCO-PUF) has recently been proposed. It is based on a differential architecture and exploits the non-linear relationship between current and voltage in the subthreshold operating region. As CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) is becoming more pronounced, resulting in reliability issues for the PUF response. Differential design techniques can be useful for mitigating and canceling out first-order environmental dependencies such as aging, temperature and supply voltage. In this study, we investigate the robustness of PUFs with differential architectures, such as TCO-PUF and Arbiter-PUF, under the influence of NBTI. Our results indicate PUFs with differential architectures are less vulnerable to aging-related degradation compared to other PUF designs such as RO-PUF and SRAM-PUF. We show that the reliability of TCO-PUF and Arbiter-PUF only degrades by about 4.5% and 2.41%, respectively, after 10 years, while RO-PUFs and SRAM-PUFs degrade by about 12.76% in 10 years and 7% in 4.5 years, respectively.

I. Introduction

Classical cryptographic primitives rely heavily on the ability to store secret information securely. For example, storing digital keys requires on-chip, non-volatile memory (NVM) such as fuse or EEPROM [1], [2]. However, fabricating on-chip NVM is expensive and difficult. Furthermore, on-chip memory is susceptible to physical attacks such as invasive, semi-invasive, or side-channel attacks, as well as to software attacks [3]. A class of novel cryptographic primitives called Physical Unclonable Functions (PUFs) has emerged as a promising technology to overcome these issues. PUF technology provides high security for identification and authentication by exploiting inherent manufacturing process variations. The complex statistical variations of transistors and interconnects in a PUF map a set of challenges to a set of responses, also known as Challenge Response Pairs (CRPs). The mapping of CRPs is unique to each PUF instance, thus, providing uniqueness, unclonability and randomness and making PUFs very suitable candidates for robust security devices.