End-to-End Modeling and Optimization of Power Consumption in HPC Interconnects

The Interconnect topology is one of the key design choices of large-scale distributed computer architectures. It might also become one of the most power consuming design elements as traffic volumes and interconnect size continue to grow. High interconnect power consumption can be simply provoked by non-energy efficient components, or can in contrast be due to architectural misconception. In this paper, we propose and combine various high-level models to realize a clear breakdown of the power consumptions, and analyze how these depend on various parameters, either external or internal, to the interconnect. Our initial results indicate that end-to-end interconnect consumption is dominated by routers. The node compute power can also affect the interconnect energy efficiency, especially if links of equal bandwidth are used as injection links and topology inner links.