Radiation-tolerant IP-cores for 2Gbps serial links for the data readout in future LHC experiments

The increase of luminosity foreseen for the future upgrades of the Large Hadron Collider at CERN will require the complete redesign of the Front-End electronics in all the experiments. One of the goals of the RD53 collaboration is the development of a full set of radiation-tolerant IP-cores in view of the design in 2016 of the first prototype of the new Front-End circuit for the pixel detectors of the ATLAS and CMS experiments. In this framework we designed radiation-tolerant 2Gbps Serializer and Deserializer modules and 3GHz differential SLVS Driver and Receiver devices in a commercial 65nm CMOS technology. IP-cores will be described and results of tests on first prototypes will be presented, including results of irradiation tests with heavy ions.