The impact of process variation and stochastic aging in nanoscale VLSI

With the down-scaling of CMOS technology into deep nano-scale era, negative-bias temperature instability (NBTI) effect becomes stochastic due to its widely distributed defect parameters. As a result, the delay degradation due to the intrinsic variability of NBTI becomes also stochastic and the matter is aggravated when it is combined with process variation. Accurate stochastic timing analysis of the circuit becomes very important in this case since over and under margining can lead to a significant performance or yield loss (timing failure), respectively. This paper proposes a flow and investigates the combined effect of stochastic NBTI and process variation on the performance of the VLSI design at the circuit level in a 7 nm FinFET technology node by abstracting atomistic NBTI models (for the stochastic behavior) to the circuit timing analysis flow.