The physical mechanism investigation between HK/IL gate stack breakdown and time-dependent oxygen vacancy trap generation in FinFET devices

In this paper, the detailed TDDB models of HK/IL gate stack for N/PMOS were established through the analysis of oxide trap generation in FinFET technology. We systematically characterized gate oxide traps of HK and IL layers by AC admittance and SILC spectrum methodologies. We found that the generation of deep traps in HK layer plays the decisive role in NMOS TDDB, while the formation of deep traps in IL and HK layers are critical to PMOS TDDB. In addition, the deep traps in HK/IL gate stack were found to be highly responsible for the permanent damage during stress, such that, the physical mechanisms of HK/IL gate stack breakdown in FinFET devices can be successfully explained through the time-dependent HK and IL trap generations. From this trap studies, we demonstrated that TDDB reliability of FinFET technology can be improved through the reduction of deep traps.