Engineering the failure-free lifetime for Cu vias

Stress induced void (SIV) nucleation and growth is studied using phenomenological creep models and used to predict failure rates in Cu/low-k via chains from a 110nm process. It is argued that the void formation is induced at grain-boundaries, triple-junctions, and microstructural changes due to the local stress concentrations and stress-gradients inducing micro-fracture and subsequent flux divergence. The longer term stress-relaxation is described by a power-law in the thermal stress. Experiments are performed to verify the impact of via adhesion, via gouging, via diameter, via placement in extensions relative to large metal leads, and geometrical variations in the metal layer. High Temperature Storage (HTS) tests completed at 125 to 250° are compared to long-term, low-temperature (30° C) data to verify the acceleration model. Our data indicates that a failure-free lifetime (FFL) may exist for certain geometries, and new scaling relationships are used to establish conditions where SIV does not impact the long-term reliability of Cu vias. A novel HTS protocol is suggested for scaling to immortal vias using the right hand side of the cumulative distribution function and model fitting to a generalized Pareto distribution, where the Pareto parameter is equal to the power-law of the stress-relaxation. The short-term and long-term HTS protocols are linked in the model, so that measurement of one can provide information about the other, allowing for the use of the distribution to establish process and design factors that ensure high reliability.