Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design

Important characteristic of any VLSI circuit is its power consumption, reliability, operating speed and silicon area. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirements. Pipelines can be used for achieving high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages should also increase and so the memory elements. These memory elements increase the area overhead and restrict the maximum achievable frequency due to their delays. Memory-less pipelines based on dynamic design address these issues but, still require high power consumption for the clock signal. In this paper we propose a sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Thus the proposed technique provides advantages over preexisting techniques in terms of power requirement, area of implementation and operating speed.