A new topology for cascaded multilevel inverters with reduced number of power electronic switches

In this paper, a new basic unit for cascaded multilevel inverter is proposed. The proposed basic unit consists of m cells. Each cell can generate three levels. The proposed multilevel inverter is based on series connection of several basic units. The proposed multilevel inverter is investigated at both symmetric and asymmetric topologies. In order to generate all voltage levels at the output, four algorithms to determine the magnitudes of dc voltage sources are proposed. Reduction of number of power switches, driver circuits and IGBTs are some advantages of the proposed cascaded multilevel inverter. Finally, to verify the correctness operation of the proposed inverter, the simulation results of a 27-level inverter based on proposed topology by using PSCAD/EMTDC software are used.