Impact of PCB Layer Orientation on the Drop Reliability of WCSP Boards

In the electronic industry the portable devices are becoming the prime factors to dominate the market share. And with the blessing of miniaturization, these devices are also becoming smaller and smaller day by day. On the other hand, with this miniaturization process these devices are becoming more susceptible to drop impact loading. To ensure product quality and to integrate more complicated functionality in these devices reliability test is very important. To meet the robust and quick production demand, manufacturers are supplementing drop/shock testing with the aid of computational simulation using Finite Element Analysis (FEA). In this paper a comprehensive study has been carried out to investigate the behavior of solder joint failure during drop impact loading due to different thickness and layer stack-ups of Printed Circuit Boards (PCBs). To do that, after evaluating the modulus of elasticity and densities for all of these boards experimentally, a computational approach has been followed to understand the nature of strain and stress generation around the interconnections by performing Finite Element Analysis on the PCB-package assembly. This study gives an insight of how the impact loading is affected by the change of layer stack-ups and thicknesses of PCB mounted with small Wafer Level Chip Scale Packages (WCSPs).