Adaptive Patterning Design Methodologies

Fan-Out Wafer-Level Packaging (FO-WLP) holds immediate promise for packaging semiconductor chips for mobile consumer electronics applications. FO-WLP enables size and performance capabilities similar to Wafer-Level Chip-Scale PAcakging (WLCSP), while extending the capabilities to include multi-device system-in-packages. With lower costs than 2.5D interposer technologies, FO-WLP can support applications that integrate multiple die and devices from heterogenous processes. FO-WLP also provides a path for shrinking die geometries without driving printed circuit boards to smaller interconnects. Industry challenges in handling cost, yield, and the requirement for high die location accuracy after placement and molding have driven innovative approaches, such as Adaptive Patterning. Adopting these new technologies for single-die and system-in-packages will require more advanced design methodologies and tools than traditionally used in semiconductor packaging. This paper describes a new technology, called Adaptive Patterning, for overcoming the die-shift challenge. In this manufacutring process, an optical scanner is used to measure the true position of each die after molding, and a uniquely generated fan-out design is applied to each package. One design technique, adaptive alignment, shifts and rotates the first via and RDL layer to match the die location. Another technique, adaptive routing, utilizes a fan-out RDL design with sections removed near vias that contact the die. The final RDL connections to the die are generated by an auto-router after the true die locations are known. This technique requires that the design is routable for all permutations of die-shift and rotation. For designs containing multiple die or devies such as system-in-packages, both design techniques can be combined. In one example, two sections of via and RDL paterns were separately aligned to two die. Connections between the RDL patterns were completed by an auto-router to handle simultaneous worst-case shifts from both die. In all techniques, the design rules are parameterized by the radial shift, a value combining the X, Y, and rotation shift components into a single magnitude. The radial shift depends on the design technique, package size, and the offset of the die from package center. During the design process, this value can be computed from empirically gathered data. This paper details these design techniques and the parame-terization of design rules using the radial shift.