Design of a gain-stage for pipelined SAR ADC using capacitive charge pump

This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-μm CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-μm CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 μW with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCP's to reach the similar gain and gain bandwidth.