Reducing logic encryption overhead through gate level key insertion

Integrated circuits (ICs) are used in fields such as banking, transportation, energy, health, and the military. However, the use of ICs in many applications is threatened by an increasing reliance on untrusted third-parties within the IC design flow. The result is a growing concern for IC reliability and security, with threats that include IC counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion of hardware Trojans. An area of research aimed at ensuring the reliability and security of ICs in critical applications is logic encryption. While the security of an IC is increased when using logic encryption, current methods such as the XOR or look-up table (LUT) techniques have high per-gate overheads in area, performance, and power. A reduction in the per-gate overhead permits the use of logic encryption in a wider range of applications. Novel gate level designs for logic encryption are described in this paper, resulting in reduced overhead in power, area, and performance as compared to the XOR or LUT based techniques. With the proposed gate level technique, encrypting an AND gate results in a power reduction of 43.2%, an estimated area reduction of 19.8%, and a performance increase of 46.9% in comparison to the XOR based implementation of the encrypted AND.