Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder

In this paper novel method for multiplier and accumulator is proposed by combining reversible logic functions and hybrid carry look-ahead adder. Modified booth algorithm produces less delay in comparison with a normal multiplication process and it also moderates the number of partial products. The Carry look-ahead adder is used for controlling the overall MAC delay. The main purpose of designing a reversible logic is to reduce the circuit complexity, power consumption and loss of information. Here we survey on possible ways to make a full adder design using different reversible logic gates. We also proposed a new hybrid CLA from the existing hierarchical CLA which exhibits high performance in terms of computation, power consumption and area. Area, delay and power complexities of the resulting design are reported. The proposed MAC shows better performance compare to conventional method and has advantages of reduced area overhead and critical path delay. This new high speed hybrid carry look-ahead adders are simulated and synthesized using Synopsys (90 nm) Design Compiler and Xilinx ISE simulator.