Enhancement of the partial discharge inception voltage of ceramic substrates for power modules by trench coating

Due to the ongoing development of high-blocking semiconductors the installed ceramic circuit boards in power modules, such as DBC (Direct Bond Copper) or AMB (Active Metal Brazed) substrates, will have to isolate high voltages (HV) beyond 6.5 kV in the near future with high lifetime and reliability. Such high blocking voltages and the correlating increased electrical field strengths induce partial discharges (PD) in the ceramic substrate as well in the encapsulating organic materials, which represent a key degradation mechanism of HV power modules. In this work a promising novel coating technology for ceramic substrate trenches, significantly enhancing the partial inception voltage (PDIV) of these substrates, is presented. The coating works as a refractive field control and reduces the field strengths in the most critical section for PD - the so-called triple point - between ceramic, encapsulate and copper metallization. Electric field simulations show a possible reduction of the electric loads in that critical area by over 10 %. Phase resolved partial discharge (PRPD) tests confirm the simulation results by significantly increased partial discharge inception voltages (PDIV) of trench coated Al₂O₃ DBC substrates (curamik® power) compared to untreated ones. Long term aging tests (1000 h @ 85 °C/85 % r. h.) on trench coated DBCs, covered with Wacker SilGel 612®, were executed to examine the robustness of this coating and to investigate the PD behavior of DBC substrates depending on the degree of aging. The novel coating looks very promising.

I. Introduction

Partial discharge (PD) is a key degradation mechanism of insulating materials in high voltage power modules. PD is caused by high electric field strengths in the vicinity of the edge structures of the installed ceramic circuit boards such as DBC (Direct Copper Bonded) or AMB (Active Metal Brazed) substrates. Especially for upcoming high-blocking (HV) semiconductors beyond 6.5 kV novel substrate technologies must be developed to withstand the electrical strains over the lifetime of power modules. A simple scaling of the ceramic thickness has two drawbacks. The specific insulating properties of the ceramic material decrease disproportionately with elevated thickness. Furthermore, the increased ceramic thickness leads to an increase in thermal resistance. Moreover, the commonly used organic encapsulation materials, applied to prevent electrical discharges in air and to protect from contamination, also have to withstand these electric field strains. Already small voids inside these coatings or wetting imperfections at interfaces provoke local electrical field enhancements, where PD may take place and damage the insulation materials. Fig. 1

Cross sections of coated DBC trenches, left: Coating with low dilution rate (left), right: Coating with high dilution rate