An efficient timing analysis model for 6T FinFET SRAM using current-based method

Accurate timing analysis is a critical step in the design of VLSI circuits. In addition, nanoscale FinFET devices are emerging as the transistor of choice in 32nm CMOS technologies and beyond. This is due to their more effective channel control, higher ON/OFF current ratios, and lower energy consumption. In this paper, an efficient Current Source Model (CSM) is presented to calculate the output waveform as well as the read/write delay of 6T FinFET SRAM cells accounting for noisy waveform at each voltage node. In this model, the non-linear analytical methods and low-dimensional CSM lookup tables (LUTs) are combined to simultaneously achieve high modeling accuracy and time/space efficiency. Experimental data shows that our proposed framework not only provides accurate results in timing analysis, but also can capture the effect of arbitrary voltage noise.