Implementation and performance analysis of single layered reversible Parity generator and Parity checker Circuits using Quantum Dot Cellular Automata paradigm

In this paper the concept of low power technology and Nanoelectronics is used while implementing the reversible logic based parity checker and parity generator circuits using Quantum Dot Cellular Automata Combination of reversible logic and quantum dot cellular automata technology provides the resultant circuit whose size is extremely small as well as the power consumption in the circuit is very less. In this paper single layered reversible parity generator and checker circuit is proposed. This parity checker and parity generator circuits are designed using efficient reversible XOR gate. Here efficient design of QCA based Feynman gate is used for the implementation of the circuits. In digital communication, a large amount of data is transmitted and received across various mediums. When data is transferred noise gets added to it which makes signal recovery very difficult. Parity bit is used to recover the signal. Parity bit is known as very common error detection code in the data transmission system. Comparative analysis of proposed reversible circuits like Parity Generator and Parity Checker Circuits are efficient in terms of area, complexity and latency and wire crossings. QCADesigner 2.0.3 tool is used for implementation of these circuits.