Design and analysis of charge pump for PLL at 90nm CMOS technology

The aim of this research is to design a charge pump to improve current matching, wide range of output voltage, fast switching operation and reduce charge sharing in transistor. The design of charge pump is proposed and simulated in cadence virtuoso ADE and ADXL tools at 90nm CMOS technology. Current mismatching is analysed with Monte Carlo simulation and output variation is calculated on PVT. The designed charge pump achieves wide output voltage swing 0.5∼1V, improve current mismatching approximate 0.5% and power dissipation of 320 µW.