Low power FIR filter implementation on FPGA using parallel Distributed Arithmetic

The Distributed Arithmetic (DA) algorithm is extensively used for FIR filter implementation based on FPGA technology compared with the earlier used MAC (Multiply and Accumulate) architectures. DA has the feature of bit-parallel data processing which makes it faster in speed and it also provide an efficient architecture in terms of power consumption and size of the system. In this brief, an architecture using parallel DA is proposed for the implementation of a 16
^th
order low pass FIR filter on FPGA. Simulation is done using ISIM which is integrated tool in ISE Design Suite 14.5 and the design is implemented on the Xilinx Spartan-6 (device: xc6slx4-3tqg144) FPGA chip. In the proposed architecture, the pipelining is used to increase the maximum frequency of the FIR filter.