Design Space Exploration of 14nm Gate All around MOSFET

As semiconductor device geometry scales down, the Short Channel Effects (SCE) are dominating. To reduce the SCE, gate oxide thickness is reduced. This leads to increase in gate leakage current. To overcome the SCE and to control the gate leakage current, Gate All Around (GAA) structure is proposed with optimum values of fin dimensions and thickness of the gate oxide. The performance of GAA MOSFET with gate oxide HfO
₂
are simulated and compared with conventional gate oxide SiO
₂
for the same Effective Oxide Thickness (EOT) and fin dimensions. It has been shown here that the performance of the GAA structure with HfO
₂
as gate dielectric is comparable with the performance of the optimized GAA structure with the traditional SiO
₂
dielectric. According to International Technology Roadmap for Semiconductors (ITRS), the EOT for gate lengths below 9.7nm is less than 0.6nm. It becomes very difficult to maintain a thin interfacial layer of SiO
₂
of around 0.5nm along with High K such as HfO
₂
, in turn it leads to increase in manufacturing complexity and cost. The threshold voltage gets affected as thickness of the gate oxide varies, but the proposed GAA structure has wrap around gate structure and thin fin width(height), which makes better electrostatic control over the channel, hence effect on the threshold voltage shift is nullified. All the simulations are performed using the 3D Sentaurus TCAD Device simulator. Here, we are concluding that proposed device structure has better performance over nominal structure with gate oxide HfO
₂
.