Design and Evaluation of an FPGA-ADC Prototype for the PET Detector Based on LYSO Crystals and SiPM Arrays

The aim of this study is to design and evaluate a simple free running analog–digital converter (ADC) based on the field-programmable gate array (FPGA) device to accomplish the energy and position readout of the silicon photomultiplier (SiPM) array for application as positron emission computed tomography scanners. This simple FPGA-ADC based on a carry chain time-digital converter (TDC) implemented on a Kintex-7 FPGA consists of only one off-chip resistor so it has greater advantages in improving system integration and reducing cost than commercial chips. In this article, an FPGA-ADC-based front-end electronics prototype is presented, and both the design principle and implementation considerations are discussed. Experiments were performed using an
$8 \times 8$
(crystal size: 4 mm
$\times $
4 mm
$\times $
15 mm) and a 12
$\times $
12 (crystal size: 2.65 mm
$\times $
2.65 mm
$\times $
15 mm) segmented LYSO crystals coupled with an
$8 \times 8$
SiPM (J-series, from ON Semiconductor) array which is under
²²
Na point source excitation. Initial test results indicate that the energy resolution of the two detectors after correction is around 13.2% and 13.5% at 511 keV, and the profiles of the flood histograms show a clear visualization of the discrete scintillator element. All measurements were carried out at room temperature (~ 25°C), without additional cooling.