SRAM cell with improved stability and reduced leakage current for subthreshold region of operation

In this paper, a Modified Differential 8T SRAM cell is proposed for subthreshold region of operation. Forward Body biasing technique is used to improve the drivability of transistors and sleep transistor logic is used to reduce the leakage current in standby mode. The proposed design is implemented with 45 nm CMOS technology and is simulated using Cadence Virtuoso Simulator. At 0.5 V supply voltage, the read SNM and write SNM are 98 mV and 112 mV respectively and these are 32% and 21% higher than there reported in literature. The leakage current and power consumption of the cell are 3.26 fA and 1.63 fW respectively.