A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

Continuous-time delta-sigma modulators (CT-DSMs) are well suited for the baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. For example, 5 downlink component carriers are no longer sufficient to meet the ITU requirement for IMT-advanced and up to 32 carriers and 640MHz RF bandwidth are under discussion for 3GPP Release 13. This increased BW drives CT-DSMs to operate at a several-GHz clock rate, but comes at a cost of higher power consumption, even when utilizing advanced nanometer CMOS technologies. Previous >100MHz-BW CT-DSMs required a 4GHz clock rate with oversampling-ratio (OSR) beyond 13× and power exceeding 250mW [1,2]. By contrast, the proposed CT-DSM decreases the OSR to 9× while consuming 40mW to achieve 72dB DR within 160MHz BW.