Overall performance evaluation of embedded microchannel cooling layers for 3D architecture chips

Modern manufacturing processes have allowed construction of 3D integrated circuits (IC) with embedded cooling. This technology has been proven to be the most effective solution for dissipating the high heat fluxes of up to 100 W/cm2 generated during the operation of 3D IC chips. Recent published works indicate that it is possible to maintain the maximum surface temperature below the allowable limits for electronic devices (358 K or 85 °C) with low pumping power requirements. A microchannel cooling layer suitable for 3D IC applications is numerically analyzed in this work. The chip area considered is 10 mm × 10 mm and the thickness of the walls between channels is 100 μm. 3 different width levels and 7 different height levels are considered. A total of 21 configurations are simulated. The total heat supplied to the cooling layer is 200 W. The volumetric flow rate is constant for all simulations and its value corresponds to the flow rate required to keep the maximum surface temperature of the base configuration (890 μm width and 100 μm height) at 85 °C. The overall performance of microchannel a microchannel cooling layer with similar geometry as the base configuration has been recommended in the literature for 3D IC applications. Results from this investigation indicate that the overall performance of the microchannel cooling layer is improved for channels with high height to width ratios. The recommended configurations lead to similar pumping powers, but the reduction in maximum surface temperature is near 35 °C as compared with the base configuration.