A New Perspective of Using Integrated On-Chip Syntonistor for Time Synchronization in Network: Meeting the TAACCS Challenge

The emergence of Internet of Everything combined with the growing transition of telecom system from traditional wired to wireless technologies have made time-awareness a feature of high priority. One of the key elements in time-awareness applications is time synchronization, which is accomplished by synchronizing the clocks of all nodes. From TDM based network having physical connection for timing signal to connectionless packet-based network, the task of synchronizing clock becomes increasingly complex. To meet this challenge, a call for innovative design on clock circuitry used in the communicating nodes is recently put forward in TAACCS (Time-Aware Applications, Computers, and Communication Systems). In this article, an emerging frequency synthesis technique with features of small frequency granularity and fast frequency switching is suggested as on-chip integrated syntonistor for periodically tuning each nodes' clock frequency, to assist the task of time synchronization. This is a new perspective since it enables the frequency of clock hardware to be tuned continuously for better synchronization quality, not just the value of time register as traditionally done. This is a multidiscipline subject involving network architecture, VLSI circuit design and computer science.