I. Introduction
In the recent years, power efficiency has emerged as one of the most critical goals of hardware design. Enormous efforts have already been devoted to improve the power consumption in various levels from algorithmic and software level down to circuit and transistor level. Emerging applications in digital signal processing, computer vision, and machine learning have created new power consumption challenges due to their high computational demands. At the same time, these applications also afford new opportunities for novel low-power implementations. In particular, the common feature of these application domains is an inherent tolerance for limited and insignificant inaccuracies. This error tolerance arises for multiple reasons, including imperfect perception in human sense, noisy input signal, redundancy in the input data or the absence of a universal best answer [1]. This inherent error tolerance can be exploited using approximate computing, which effectively allows designers to trade off computational accuracy for savings in power consumption and computational complexity.