Implementation Of 64Bit high speed multiplier for DSP application- based on vedic mathematics

In modern days Digital Signal processors are one of the fastest growing segments as it has many applications in the various fields of engineering disciplines like Audio Signal Processing, Image Processing, wireless application etc. Like all other processors, a successful DSP processor should have maximum speed, higher code density and low power. For many DSP application specific processors speed is the major concerned parameter compared with other useful parameters like area and power. In the frequently used functions like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), multiplication is the important function carried out internally. When we consider the speed of execution of these functions, the easiest way for the improvement is to enhance the performance of the multiplier units. Thus the implementation of fast multiplier will improve the performance of the current processors. Vedic mathematics based on ancestral Indian Vedas gives a different multiplication algorithm to carry out fast multiplication. In emerging technological world the data handling capacity is an important factor. So the implementation of a high end processor can make significant impact in the technological world. This paper proposes a new architecture for high end processor which gives better performance than existing architectures. In this work digital coding is done in Verilog HDL, synthesis of the design is done by using Xilinx ISE 14.7 and Cadence encounter RTL Compiler. Analysis of implemented digital system is done by using powerful cadence tool Encounter. Finally in this paper we analyse how speed and area changes when the number of bits increases.