Analysis and Modeling of One-Dimensional Folded Vertical Hall Sensor With Readout Circuit

A Simulation Program with Integrated Circuit Emphasis macro model is proposed to simulate and understand the interaction between magnetoresistor (MR) and vertical magnetotransistor (VMT) in the proposed 1-D folded vertical Hall sensor (VHS), which was fabricated with 0.18-μm 1P6M CMOS technology. In the proposed net-list file, the resistor MR enhances the linearity and the transistor VMT improves the magnetosensitivity between the induced Hall voltage and the applied magnetic induction. The folded design effectively eliminated the coupling Hall voltage that was generated by the Lorentz force. A readout circuit composed of a noninverting amplifier, low-pass filter, and instrumentation amplifier was also designed to enhance the magnetosensitivity, with a gain of 43 dB. Simulated and measured results verify the accuracy and flexibility of the proposed folded VHS. Measurements revealed that the maximum output Hall voltage VH, optimum supply currentrelated magnetosensitivity, mean nonlinearity error, smallest offset, and relative bias current were 6.911 mV, 92.15 V/(A·T), 10.26%, 42.61 mV, and 5 mA, respectively, for the proposed folded VHS with readout circuit at a load capacitor of 10 pF and a supplied voltage of 1.8 V. The VHS had good supply currentrelated magnetosensitivity because of the gain of the readout circuit.