A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit (IC) has been implemented for a bridge sensor. The read-out IC has a capacitively coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta–sigma (
$\Delta \Sigma)$
analog-to-digital converter (ADC) with an output data rate (ODR) of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The
$\Delta \Sigma $
modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoIs) filter. Implemented in a 0.13-
$\mu \text{m}$
CMOS process, the read-out circuit achieves an input impedance of 22
$\text{M}\Omega $
at a data rate of 800 SPS, a sensor offset compensation range of ±350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of
$1.72 \mu \text{V}_{\text {RMS}}$
at a gain of 128. It draws an average current of
$106.3 \mu \text{A}$
from a 3-V supply and
$1.3 \mu \text{A}$
from a 1.5-V supply.